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DRC rules affect Copper Pour Rules

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4件のコメント

  • Boss .

    Hello Jan, yes the copper pour obeys the design rules as it is a 'shape'. I think the confusion here is, a copper pour can be any shape and on any layer, so you can create your own 'power planes'.
    You can also have a dedicated power plane that DSPCB creates which uses the Power Plane settings as defined in the rules.

    Creating your own power plane using a copper pour allows flexibility as you can split it to have several power plane areas such as analog (low noise) and digital or even power which will have more electrical noise and you can even add tracks if required, whereas as DSPCB expects a power plane to be a complete layer of copper as with a full power plane.

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  • Jan Kratochvil

    Hello Boss,

    thanks for explanation, but I think it is still a bit confusing. Rules for power plates are effective only if defined clearance is lower than value specified in DRC clearance. For example if the clearance for DRC is 0.15mm and the rules for power plates is 0.25mm then 0.15 is applied for copper pour. I think, that defined clearance for DRC has nothing to do with rules for copper pour. DRC should be for checking only not to affect behaviour like copper pour. This is like mixing apples with oranges. I understand your explanation about multiple power plates, but it is different story. If I used regular polygon as power plate, then I'm expecting that rules for DRC will be applied if I used "DRC check" or "Online DRC". In other situation, when simple two layer board is designed and all of "empty" space is poured with copper typicaly connected to GND I expecting copper pour will be poured according to defined rules for power plates - but it will not if clearence for DRC are lower. I think that there are two issues - one can be called "what is power plate (copper pour / polygon)" and second "usage of DRC check clearance for power plates (copper pour)". Perhaps I was able to explain it better.

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  • Brad Levy

    Jan, in DS PCB, a power plane is defined as a PCB copper/electrical layer dedicated to a particular electrical (like ground) associated with it. A shape on a regular layer is not considered a power plane, regardless of whether the shape is a regular polygon or a copper pour. 

    Historically (on the older, mechanical photo-plotters) power planes were generated negatively compared to regular planes. On a regular plane, the film was exposed to light through apertures in areas where the copper was to be. On power planes, the film was exposed in those areas where the copper was to be etched away instead, since those represented a much smaller portion of a layer that was intended to be all one network, and could be easily defined with a smaller amount of data, and plotted much faster than drawing all the lines to "color in" the power plane.

    With faster processors for CAD, bigger storage media, and digital photo-plotters where processing time where no longer closely coupled to drawing complexity, arbitrary copper pours became more feasible and common, and are used for other reasons in addition to large power or ground areas. (Other reasons include thermal conduction and evening out average copper density across the board for more consistent etching.)  So it wouldn't be appropriate for DS PCB to assume you want power plane rules applied to all copper pours.

    I think it is wrong to think of the Spacings as only for DRC. They reflect the technical constraints of the process you intend to use for manufacturing. In some cases, DS PCB can act on them as you are drawing, pouring, or autorouting. In other cases, it is more feasible user-interface or interaction-speed wise to Let you place things without constraint, and do the checking against the constraints as a separate later step (DRC). 

     

     

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  • Boss .

    Hello Jan,

    Brad has given a good overview and just to reinforce this, where you said
    "In other situation, when simple two layer board is designed and all of "empty" space is poured with copper typicaly connected to GND I expecting copper pour will be poured according to defined rules for power plates - but it will not if clearence for DRC are lower."

    This is your main confusion, you are pouring copper on a "signal" plane and it will obey the rules as set up in the spacings rules. The copper pour will be 'painted' onto the layer avoiding pads, vias, tracks etc. as defined by your settings.

    Regarding a "Power plane" this is a separate layer(s) normally in a 4 or greater layer board. It is generated automatically according to the power plane rules on these specific layers. No copper pour is involved in this process.

    For your type of design applying a copper pour use the Spacings Rules as these are the settings used for all signal layers.

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