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PCB wire links & Track to Pad errors

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  • Brian Keen

    I've found a possible solution - although it's a bit clumsy...

    First I change all the pads associated wire links to have a smaller diameter such that the T-P errors go away (e.g. 50 tho'). This leaves plated through vias with small pad sizes.

    Then I add larger pads (e.g. 100 tho') to the copper side layer of the PCB only directly beneath each of the wire link vias.

    At this point the pads and vias are separate: If you move one of the copper side pads, the associated vias remain in their original position. To get around this, you can link pairs of vias and pads together in groups. To do this you have to first move the copper side pad out of the way. Then you can select both the pad and the associated via at the same time and create a new group with the 'tight group' initially unchecked. That allows you to move the copper side pad back to it's original position directly beneath the via. Then you can modify the group properties and check 'tight group'. From now on, when you move the copper side pad or the via, both move at the same time.

    The only problem I've found so far is that the drill holes in the copper side pads beneath the vias appear filled in when using the 3D view.

    Is there a simpler way?

     

     

     

     

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  • Brian Keen

    My attempted solution above doesn't work as well as I had hoped!

    It removes the T_P errors (provided you connect the copper side pad to the same net as the associated via).

    However a Design Rule Check gives Drill Hole To Drill Hole (D-D) errors.

    I'm still trying to find a solution.

     

     

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  • Boss .

    I have looked into this in the past (even for matrix board) and you can get so far with a solution, but you have to accept a compromise somewhere. As you are using copper tracks to simulate links then the DRC will check against all the normal rules that are enabled.

    What can be done then? First you can set the top copper links style to something really small, that is just visually OK. Then set the grid snap to something that is OK for the DRC spacing rules and do a copper track that navigates around pads that are in the path. This will at least let you check nets against the schematic.

    You can draw the actual link path on the silkscreen or documentation layer ad switch off the top copper if you want the image to look nice for documentation.

    I also created a "Link" component and the footprint had options for 0.1" pitch upwards (to aprox 1.5"), it works but difficult to use in practice as you have to measure the link span before adding the component and even when it looks 'nice' the SCH and PCB nolonger match regarding nets or the component, and you may also introduce component to component errors.

    I investigated pads with small or zero pad areas on top copper and normal width on the bottom copper, i.e. two SM pads with a drill hole, so not wildly different from what you have done, but once you do this they are two pads with a common drill (overlaping) hole, so again a DRC error....
    You can group these pads and copy and paste as required, and then ignore the drill hole DRC or uncheck it.

    Interestingly I noticed the new 'PRO' has 'wire links', but have not investigated further.

    Below is an image showing what I mentioned above.

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