メインコンテンツへスキップ

2 PCB Layout Questiond

コメント

14件のコメント

  • Brad Levy

    RE: Missing thermal spokes. What net is the area pour on Layer 2? What net(s) are the vias or through-holes that are missing the thermal spokes?   If they aren't the same as the pour, then adding thermal spokes would mean the nets would be shorted together - not good if they aren't the same net.

    For example, a frequent practice is to make two of the inner layers (primarily) power and ground planes, one being assigned to the ground net, the other being assigned to the predominant supply net (+5, or +12, for example). I say "primarily" because you may have a few isolated traces routed on these layers as well, but most of the routing is being done on your outer layers. Also, your power plane might be split into several separate pours, one for each of multiple supply voltages, or one for power supplying the digital circuits and another (hopefully lower noise one) supplying the analog circuits. If a through-hole signal is assigned to the same net as the pour on an inner ground plane, DS PCB will connect the through-hole to the inner plane, either directly or using thermal spokes, depending on what you have selected. So a through-hole assigned to the ground net will get connected to the inner plane pour also assigned to the ground net, but will be left unconnected to an inner plane pour assigned to the +5 net.

    0
  • Richard Caldwell

    Brad:

    Your are very right about one plane being positive and the other is ground plane to form a high frequency filtering cap. In the design I am working all 4 layers are GND planes. The reason is there will be high currents pulses, so the planes will help  disprove over a large area. Also the lay out of the PCB there is not enough real estate for a GND  trace. So I am also using the plane as the GND trace.

    The missing thermal spokes (connect to GND missing) are components throught-holes. All the other layers there is thermal spokes (attached layer 3 thermal-spokes screen capture pic).

    Yes I triple check that all signals are correct an not shorted out.

     

    0
  • Brad Levy

    I just tried it out here and it seems to be working okay, using 8.0.
    You do need to be aware that if you are including other signals or keepouts on the inner planes, they need to be defined as a regular planes, not as type Power in the Bias of the Design Technology. A proper example:


    Then define copper pour areas on each layer defining those portions you want to become ground plane.

    These settings for the copper pour worked in my test:

    Note the Net assignment on the Shape tab of the copper pour properties, and the checked items on the Area tab.

    Also remember need to unpour then repour if you make changes to any vias or through holes, in order to correctly regenerate the pour. Do that for each of the pour areas.

    -Brad

    0
  • Brad Levy

    As far as the component that claims to have twelve pins even though you think it should only have nine:

    This is sometimes the case as a side-effect of the way the PCB footprint has been defined.

    You will find it most frequently in unusually shaped packages, packages with mounting tabs, or packages for switches or relays that are available with different subsets of contacts present but all on a common pinout. For example, the layout of a SPDT relay may have the coil and contacts in the same locations as the coil and first set of contacts of a DPDT relay in the same family, but with the second set of contacts (which are present in the DPDT version) omitted. If you look at the manufacturer's data sheet, they frequently try to keep the signal numbers the same for contacts that are present in both versions. That way things don't get muddled if the relay plugs in to a socket, and the end product may be shipped with either relay depending on the application.

    Sometimes a package may be similar to a dual-in-line package, but with wider spacing between the pins on one side than on the other. The person who laid out the PCB footprint may have started with the standard duil-in-line package, then just deleted the intervening pins that are not present because of the wider spacing. If they don't go back and renumber the pins, the pin count will include the pins they skipped over/deleted.

    This can be dealt with in the component's mapping table which maps which schematic pins correspond to which PCB pins. Note that you can also specify that multiple pins of the PCB footprint map to the same schematic pin number, as in the case shown below where several pins of the package are attached to the same grounded shell of the switch.


    About the only inconvenience is when you are defining which package(s) a component is available in, you need to expand your search to include the larger number of pins in the target package's footprint. Also, there are two different forms of assigning multiple PCB pins to the same schematic pin. The + method used here indicates that pins 5 and 6 are tied together within the physical component. The other method, using a comma instead of a +, indicates that the pins are not internally connected with the package, so each of the multiple pins must have its own trace to the net of the schematic pin. This is frequently the situation with supply voltage pins of an IC.

    0
  • Richard Caldwell

    I don't think but know because I drawn it and it has 9 pins. It is not a component but a edge connector. with both Power and Logic Level selectors (by jumpers).

     

    0
  • Brad Levy

    Open the PCB footprint and check the numbering on the pins. If you deleted some, then added them back, you may have nine pins but they may not be consecutively numbered - for example, 1 2 3 4 5 6 10 11 12. If so, try renumbering the pins in the footprint to be consecutive. If not, upload the component or email it to me (brad@bradlevy.com) and I'll see if I can figure out what is going on.

    -Brad

    0
  • Richard Caldwell

    Brad:

    I could not upload the component here in the forum so I sent to you by email.

    0
  • Stephen Hughes

    Just a thought on your component, it looks to me as if it's got 9 SMD pads and 3 either vias or small through-hole pads. That would make 12 - the ones on top of each other aren't joined in to a single pad.

    This would explain the pad-to-pad DRC errors you are getting as well.

    0
  • Richard Caldwell

    Stephen:

     

    Bingo. You where right. I put the VIAs to form a plated hole and a soilder pad on the bottom. After I deleted the VIAs the pin count came correct [shown in screen shot].

     

    So the question how do I draw a pad on the bottom layer? I noticed the hole is only shown on the top layer. The other layers do not show the hole or a isolation ring around the hole. 

    Thanks

    Richard

     

    0
  • Brad Levy

     

    Richard, you can set which layers the pad appears on using the Layer drop-down in the Pad Properties dialog.
    (Right click on the pad, select Properties, then click on the Layer: entry of dialog that pops up, and select [All] in the dropdown menu:

    -Brad

    0
  • Richard Caldwell

    Thanks for the info. I just want the hole to act like a VIA. Plated so it is attached to all the layers. So I can use this hole to pass a signal trace to other layers.I have placed a VIA on each pad to archive this..

     

    0
  • Stephen Hughes

    From memory you can have overlapping holes provided they are tied to the same schematic pin, so if the top pads were 1-3 and the vias were 4-6 you'd put 1+4, 2+5 and 3+6 in the component.

    Otherwise, add vias in the design rather than component, however you'll get DRC errors this way.

    0
  • Richard Caldwell

    The wisdom of this forum is way better then the manual or the tutors.

     

    Again thanks for sharing your wisdom.

     

    Richard

    0
  • Brad Levy

    As long as the Layer for a through hole pad is set to [All], it should connect to any planes or copper pours assigned to the same net. It doesn't need to be categorized as a via to do that.

    -Brad

    0

サインインしてコメントを残してください。