I have some high power LEDs on a client's design. The PCB is 2-layer with thick copper top and bottom and I need to get he heat out.
I added the thermal vias to the symbol because I have a lot of LEDs and I didn't want to add 1400 vias manually if I could help it. My current component PCB symbol (for the simplest LED) looks like this, some of the others have to be rather more complicated shapes:
The white pads are the manufacturer's recommended pads. The red and blue areas are filled copper shapes on the top and bottom layers of the PCB symbol. The slot in the top shape is where the anode connection track comes in to the T pad (so that's why you can see the bottom layer in blue beneath) The slightly larger rectangular pad is the cathode where the most of the heat comes out. so that is overlaying the cathode pad. I have added though-hole pads to connect the top layer to the bottom layer.
The problems I have are:
* I need the whole area including thermal through-hole pads to be covered by solder mask (all matt black, the PCB has to be visually non-reflective) but I can't find a way to cover them with solder resist - that only seems to apply to vias. I really don't want them shiny. (The holes are too big to tent because the board is thick, I'd like to do it without plugging the vias if I can).
*The design rule check runs so slowly that it becomes hard to use. I have 45 of these LEDs, each has 30-40 vias which makes a list of around 1400 Pad-Shape errors which is a lot to sign off. (I prefer to actually fix errors so that I know messages are significant).
* I get track to shape spacing errors where the tracks on the top copper track across the shape to reach the LED pads.
I think some of these problems might be reduced if I used copper pours instead but I really want the thermal areas to be identical for each LED type and some of them are pretty complicated to create and align accurately so many times which is why I'm trying to do it in the footprint.
So my questions are:
- What is the normal way to design heat-conducting vias and is there a good way to do it in DSPCB Pro? I know that I can actually ignore most of these errors by not checking for them but I don't want to miss errors on the rest of the board.
- Is there a way to design the pads so that they are part of the footprint that doesn't cause the spacing errors?
- What would be the best way to cover as much of the holes as possible with the solder resist if tenting isn't an option? I think maybe reducing the size of the annular ring would at least help...
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