Hi, I have use technology of fine tech in my PCB layout. Then use auto route button to get fully routed nets. I am sure the route has completed 100%. Then I use design rule check, I get a lot of errors like this "Silkscreen shape overlaps via.
Via to Silkscreen error (V-S) at (7.311 9.034) on layer "Top Silkscreen"."
What should I do to resolve this problem and why this will happen even I use only autoroute in my PCB layout?
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