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WARNING: Schematic/PCB Check... DOES NOT WORK correctly


7 Kommentare

  • Jayx .

    Hi Rolf,

    It actually does work. I think the problem you've demonstrated is caused by the fact that if you delete part of the track in fact it doesn't split the net. That's why Schematic/PCB check says it's fine, to detect this issue you have to use "Net Completion" check from DRC checks.

    Also it can be made more obvious if you select "Delete Track Does Unroute" in the Preferences. In this case, if you delete the track it will leave a thin line, like the one before routing:

  • DesignSpark PCB

    Thank you JayX for an excellent description of this issue.

    In V8 the "Delete Track Does Unroute" is selected as the default install setting so this should help most users as that is the normal desired function.

    The Sch/PCB check will return the "designs are the same" even if there are still unrouted tracks as it is not a check on routed tracks, but a useful check during the design process.

    The DRC should be performed as JayX suggests as the final design checks and all reported 'issues'  confirmed as whether they are acceptable or not.

  • Rolf Ostergaard

    Thanks. That helps a bit.

    But actually not even the "net completion" check in DRC will find a gap in all cases. 

    I have an open support ticket for this - and two different boards in the lab where missing traces were not found before manufacturing due to this problem.

    Glad to see however that the intent is that it should work and the "Delete does unroute" setting as default is a good start.

    Users of V7.2 and earlier still needs to watch out and I suggest a manual check net by net between schematic and layout.

    (I have not completed any design on V8.0beta yet.)

  • Rolf Ostergaard

    Update: Just loaded one such design into V8.0 beta R4 and the error is still there. Not even DRC will find the gap in nets.

  • Boss .

    Hi Rolf,

    I have played around with this and get the same results as JayX in V8 beta4. In Help for Schm/PCB check it does state to look at Net completion and unconnected pins in the DRC.

    If you have tried an old V7 design in V8 and do not get the DRC report that would indicate that your V7 design has the fault embedded within it.

    If it is a new V8 design was it similar to what you posted? My tests were with a few TH capacitors.

    The other thing I found in V7 is although Fwd Design Changes did not reinstate the deleted rats nest wires "Opimise Nets" does.
    However the new 'unroute' default for the delete key in V8 seems to resolve the issues for me.

    Looking in Help for some clarification.
    The Schematic PCB Check states...Schematic/PCB Check

    Whenever manual alterations to the schematic or PCB are necessary, it is relatively easy to make some on-the-fly modification to the schematic or PCB (or both) and get them out of step. This is where the Schematic/PCB Check becomes useful. The checker compares copies of the netlist for the schematic and PCB designs. The result is a report which lists any discrepancies found. This should enable these faults to be found and corrected , but you should also see the sections relating to other types of net faults. For example the PCB design Net Completion Report and the Schematic design Unconnected Pins report.

    Which implies it's not a final check as I presumed, but an 'aid' during editing.

    It also states the DRC reports/checks which should be done and I find these do report the missing connections.




  • Boss .

    I just completed one further test.

    In V7.2 I deleted the track and saved this in the project.

    In V8 beta4 I loaded the project and the DRC reported the gap in the net.

    My design had the track 'missing' from the component pads.

    I repeated this with the track having vias to the the bottom layer and that too behaved correctly reporting the gap.

  • DesignSpark PCB

    This issue cannot be replicated so it may be a corruption issue with the design, although Rolf reports a previous occurrence, so this may implicate a library component error or corruption. It has been referred to the developers for examination.


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