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PCB Routing keepout zones


6 Kommentare

  • Boss .

    As far as I'm aware power planes are just for a simple layer of copper.

    If you require tracks and keep out areas then the layers 2 and 3 should be normal layers and use a copper pour.

    I read that historically the power plane layer was created ti produce a low file size design and a copper pour is recommended for modern designs which require more flexibility such as tracks,

  • J R

    Originally layers 2 and 3 were normal layers and I attempted to use pour copper however encountered a problem, I could not control the isolation gap.

    When pouring copper there must be a minimum of .062 clearance around pads / vias that are high voltage. I could not figure out how to achieve this.

     The parameter in the pour copper dialog doesn't appear to actually change the gap.

    My sequence:

    Add > Copper pour area > polygon

    draw poly on layer and escape

    right click poly > pour copper > select net (gnd) > set isolation gap: .060 > click "OK"

    The copper pours with isolation gap of  .015 which I believe to be from the design technology "Spacings" table.

    What is the correct method to pour with defined isolation gap?

    Thanks, JR



  • J R


    I have two posts going, your last response is more to my other post.


    So let me get back on track! 

    Simply, how are keep out areas created such that the auto route is prohibited to place traces in these keep out areas, keeping in mind the area must be applied to all four layers ?

    Thanks, JR


  • Boss .

    Keepout is a copper pour function only as you discovered. The only way I am aware of stopping the autorouter using an area is to place a shape/outline/track on the top and bottom layers to act as a barrier, then performing the auto route and then removing the barrier.

    If you wish to remove copper from a power plane then as said use a copper pour. Others may have a method but from memory someone who tried to split a powerplane as analog and digital grounds ran into issues.

  • Boss .

    I just found this in my copies/notes posted by BradLevy which you may wish to explore. I haven't got the whole post but it will hopefully help.

    Brad any further comments?

    It appears that DS PCB treats power planes as filled by default, and reverses the sense of the keep-out flag on copper pours added to a power plane. So if you make a copper pour on a power plane, it actually becomes a copper keepout area on the power plane, unless you check the Keep-out Area box on the properties of the copper pour area. So to make your split plane on a plane flagged as a power plane, you would add a copper pour (not flagged as keep-out, but which would be treated as keep-out) to separate the split areas. But then, both of the areas split by the pour would still be considered the same net - which is not what you want with two different Vcc voltages. You could then define pours for the two different Vcc regions, with keep-out flagged (which would then be treated as non-keepouts, since it is on a power plane), and assign them to different nets. But even though part of the software changes behavior on a power plane, the part for drawing thermals still thinks it is a keep-out, not a regular pour, and omits the thermals. So your plane would be there, but not connected to your other layers. (At least as far as the on-screen display goes - I haven't examined the gerbers.)

    So I would definitely take the approach of making that inner layer a regular plane instead of a power plane. Which is easy to do, without starting over on your design. Just go to Settings > Design Technology, select the Layers tab, and change the Bias column of the power plane in question from Power Plane to None. Click OK. Then make your two copper pour areas on the plane (one for each of the Vcc voltages, and assigned to the corresponding nets), with Keep-out unchecked in the properties.

    Note there is one case where I can see using copper pour on a standard power plane. That is where you want the copper omitted under some section(s) of your circuitry (for example, under an antenna(s)). Just remember that as long as the Bias for the plane in the layer settings is set to Power Plane, you want to make sure that pour keep-out areas for that layer have the Keep-out property unchecked instead of checked.
    But you could just as easily set the bias to None, define a copper pour covering the entire board on that plane (with Keep-out unchecked), then define your keep-out areas with the Keep-out property checked. Which I think would be easier to keep straight in my mind.

    This "inner plane Bias as None instead of Power Plane" approach is what I'd also do for a board with analog an analog ground plane and a digital ground plane on the same layer connected at only one spot. I'd make the two planes with copper pours, then add a trace or shape at the spot I want them connected. This connection between the two will show up in the DRC, but (I think) only as one error, which you can expect and ignore.


  • J R

    Good information, the path is clear now - thank you!


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